chipsalliance/UHDM
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
In plain words
Outside PRs: 10 in 10 merged. First reply usually within 56 min.
Outside PRs merged
100%
12 merged, 0 closed, 0 still open
Higher than 82% of 565 other measured repositories
First human reply
56 min
median of 12 outside PRs, 0 unanswered
Time to merge
56 min
12 of 12 outside PRs merged
Outside PRs opened 30 to 120 days ago, so each has had time to be answered. A figure needs at least 5 pull requests, otherwise it reads "Not enough data". How this is calculated · A number looks wrong?
Your first steps here
If you have never contributed to this project, do these in order.
- 1
Read the README
No contributing guide was found, so the README is where setup is explained.
Open the README - 2
Find something small
No first issue is free right now. Look for a typo, a missing test or an unclear error message, or ask where help is wanted.
Browse open issues - 3
Know where to ask
No chat was found. Ask on the issue you are working on; that is where maintainers look.
- 4
Open a small pull request
Link the issue in it. A first reply here usually takes 56 min; until then, silence is normal.
What happens to an outside pull request
Every pull request opened by someone outside the core team, 30 to 120 days ago.
- Opened by outsiders12100%
- Got a human reply12100%
- Merged12100%
Time to first reply
After 2 days, 92% of outside PRs had a reply from a person. After a week, 100%. Bots do not count.
The last 52 weeks
Outside pull requests opened each week, and how many of them have been merged.
Starter issues
Issues labelled for beginners, with their real state. Available means open, unassigned, no linked pull request, nobody has claimed it in the last 14 days, and it was updated in the last 60 days.
No open issue carries a beginner label.
Issue replies: first human reply in Not enough data (median of 0 issues).
How to start
- Contributing guidenot found
- Code of conductfound
- Issue templatesnot found
- Dev container for one-step setupnot found
- No CLA or sign-off requirement was found.
Where the project talks
No chat or mailing list link was found in the README or contributing guide.
Activity
- Commits, 90 days
- 49
- Releases, 12 months
- 1
- Active maintainers
- 1
- Last push
- 4 Oct 2026
Stack
Badge and feed
Two ways to use these figures outside this page.
For maintainers: a README badge
Shows newcomers how quickly this project answers and how often it merges. Paste the line into your README; the badge updates with the index.
[](https://contributable.vercel.app/repo/chipsalliance/UHDM)[](https://contributable.vercel.app/repo/chipsalliance/UHDM)For contributors: follow new issues
Add the feed to a feed reader (Feedly, Inoreader, Thunderbird) and you hear about new free starter issues here without checking the site.
https://contributable.vercel.app/feed/repo/chipsalliance/UHDMFor developers: every figure on this page as JSON at /api/v1/repos/chipsalliance/UHDM.
Similar repositories
Same main language (C++), most shared frameworks and topics first, then the faster reply.
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles
- First reply
